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RM7000TM Microprocessor with On-Chip Secondary Cache Datasheet Released
RM7000
RM7000TM Microprocessor with On-Chip Secondary Cache
Datasheet
Proprietary and Confidential
Issue 1, January 2001
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use Document ID: PMC-2002175, Issue 1
RM7000TM Microprocessor with On-Chip Secondary Cache Datasheet Released
Legal Information
Copyright
(c) 2001 PMC-Sierra, Inc. The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers' internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc. PMC-2002175 (R1)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage.
Trademarks
RM7000 and Fast Packet Cache are trademarks of PMC-Sierra, Inc.
Contacting PMC-Sierra
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com
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Revision History
Issue No.
1
Issue Date
January 2001
ECN Number
3618
Originator
T. Chapman
Details of Change
Applied PMC-Sierra template to existing MPD (QED) FrameMaker document. Changed IP register bits to INT. Updated Notes 1 and 5 of the System Interface Parameters table.
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Document Conventions
The following conventions are used in this datasheet: * * * All signal, pin, and bus names described in the text, such as ExtRqst*, are in boldface typeface. All bit and field names described in the text, such as Interrupt Mask, are in an italicbold typeface. All instruction names, such as MFHI, are in san serif typeface.
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Table of Contents
Legal Information ...........................................................................................................................2 Revision History .............................................................................................................................3 Document Conventions .................................................................................................................4 Table of Contents ..........................................................................................................................5 List of Figures ................................................................................................................................7 List of Tables .................................................................................................................................8 1 2 3 4 Features ..................................................................................................................................9 Block Diagram .......................................................................................................................10 Description ............................................................................................................................11 Hardware Overview ...............................................................................................................12 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 CPU Registers .............................................................................................................12 Superscalar Dispatch ...................................................................................................12 Pipeline ........................................................................................................................13 Integer Unit ..................................................................................................................14 ALU ..............................................................................................................................15 Integer Multiply/Divide ..................................................................................................15 Floating-Point Coprocessor ..........................................................................................16 Floating-Point Unit .......................................................................................................16 Floating-Point General Register File ............................................................................16
4.10 System Control Coprocessor (CP0) .............................................................................17 4.11 System Control Coprocessor Registers .......................................................................18 4.12 Virtual to Physical Address Mapping ............................................................................19 4.13 Joint TLB ......................................................................................................................20 4.14 Instruction TLB .............................................................................................................20 4.15 Data TLB ......................................................................................................................20 4.16 Cache Memory .............................................................................................................21 4.17 Instruction Cache .........................................................................................................21 4.18 Data Cache ..................................................................................................................21 4.19 Secondary Cache ........................................................................................................23 4.20 Secondary Caching Protocols ......................................................................................24 4.21 Tertiary Cache .............................................................................................................24 4.22 Cache Locking .............................................................................................................26 4.23 Cache Management .....................................................................................................26 4.24 Primary Write Buffer .....................................................................................................27 4.25 System Interface ..........................................................................................................27 4.26 System Address/Data Bus ...........................................................................................28 4.27 System Command Bus ................................................................................................28 4.28 Handshake Signals ......................................................................................................28 4.29 System Interface Operation .........................................................................................29
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4.30 Data Prefetch ...............................................................................................................31 4.31 Enhanced Write Modes ................................................................................................32 4.32 External Requests ........................................................................................................32 4.33 Test/Breakpoint Registers ............................................................................................32 4.34 Performance Counters .................................................................................................33 4.35 Interrupt Handling ........................................................................................................35 4.36 Standby Mode ..............................................................................................................37 4.37 JTAG Interface .............................................................................................................37 4.38 Boot-Time Options .......................................................................................................37 4.39 Boot-Time Modes .........................................................................................................37 5 6 7 8 9 Pin Descriptions ....................................................................................................................39 Absolute Maximum Ratings1 ................................................................................................43 Recommended Operating Conditions ...................................................................................44 DC Electrical Characteristics .................................................................................................45 Power Consumption ..............................................................................................................46 10.1 Capacitive Load Deration .............................................................................................47 10.2 Clock Parameters ........................................................................................................47 10.3 System Interface Parameters ......................................................................................48 10.4 Boot-Time Interface Parameters ..................................................................................48 11 Timing Diagrams ...................................................................................................................49 11.1 Clock Timing ................................................................................................................49 12 Packaging Information ..........................................................................................................50 13 RM7000 Pinout .....................................................................................................................51 14 Ordering Information .............................................................................................................53
10 AC Electrical Characteristics .................................................................................................47
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List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Block Diagram ..........................................................................................................10 CP0 Registers ...........................................................................................................12 Instruction Issue Paradigm .......................................................................................13 Pipeline 1 ...................................................................................................................4 CP0 Registers ...........................................................................................................18 Kernel Mode Virtual Addressing (32-bit mode) .........................................................19 Tertiary Cache Hit and Miss .....................................................................................25 Typical Embedded System Block Diagram ...............................................................28 Processor Block Read ..............................................................................................30 Processor Block Write ..............................................................................................31 Multiple Outstanding Reads ......................................................................................31 Clock Timing .............................................................................................................49 Input Timing ..............................................................................................................49 Output Timing ...........................................................................................................49
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List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Instruction Issue Rules ...............................................................................................12 Dual Issue Instruction Classes ...................................................................................13 ALU Operations .........................................................................................................15 Integer Multiply/Divide Operations ..............................................................................15 Floating Point Latencies and Repeat Rates ...............................................................17 Cache Attributes .........................................................................................................26 Cache Locking Control ...............................................................................................26 Penalty Cycles ............................................................................................................27 Watch Control Register ...............................................................................................33
Table 10 Performance Counter Control .....................................................................................34 Table 11 Cause Register ...........................................................................................................36 Table 12 Interrupt Control Register ...........................................................................................36 Table 13 IPLLO Register ...........................................................................................................36 Table 14 IPLHI Register ............................................................................................................36 Table 15 Interrupt Vector Spacing .............................................................................................37 Table 16 Boot Time Mode Stream .............................................................................................38 Table 17 System interface Pins .................................................................................................39 Table 18 Clock/control interface Pins ........................................................................................40 Table 19 Tertiary cache interfacePins .......................................................................................41 Table 20 Interrupt Interface Pins ...............................................................................................42 Table 21 JTAG Interface Pins ....................................................................................................42 Table 22 Initialization Interface Pins ..........................................................................................42
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1
Features
* Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance * 200, 250, 266, 300 MHz operating frequency * >500 Dhrystone 2.1 MIPS @ 300 MHz High-performance system interface * 1000 MB per second peak throughput * 125 MHz max. freq., multiplexed address/data * Supports two outstanding reads with out-of-order return * Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9 Integrated primary and secondary caches -- all are 4-way set associative with 32 byte line size * 16 KB instruction, 16 KB data, 256 KB on-chip secondary * Per line cache locking in primaries and secondary * Fast Packet CacheTM increases system efficiency in networking applications Integrated external cache controller (up to 8 MB) High-performance floating-point unit -- 600 MFLOPS maximum * Single cycle repeat rate for common single-precision operations and some double-precision operations * Single cycle repeat rate for single-precision combined multiply-add operations * Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations MIPS IV Superset Instruction Set Architecture * Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution * Single-cycle floating-point multiply-add Integrated memory management unit * Fully associative joint TLB (shared by I and D translations) * 64/48 dual entries map 128/96 pages * Variable page size Embedded application enhancements * Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and threeoperand multiply instruction (MUL) * I&D Test/Break-point (Watch) registers for emulation & debug * Performance counter for system and software tuning & debug * Fourteen fully prioritized vectored interrupts - 10 external, 2 internal, 2 software Fully static CMOS design with dynamic power down logic RM5271 pin compatible, 304 pin TBGA package, 31x31 mm
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Block Diagram
Figure 1 Block Diagram
Extenal Cache Controller On-chip 256K Byte Secondary Cache, 4-way Set Associative Secondary Tags Set A Primary Data Cache 4-way Set Associative Secondary Tags Set B DTag DTLB Secondary Tags Set C ITag ITLB Secondary Tags Set D Primary Instruction Cache 4-way Set Associative
A/D Bus Pad Bus
Store Buffer Write Buffer Read Buffer
Pad Buffer Address Buffer
Prefetch Buffer Instruction Dispatch Unit F Pipe Register M Pipe Register
F-Pipe Bus M-Pipe Bus
D Bus
Floating-Point Control
Floating-Point Load/Align Floating-Point Register File Packer/Unpacker Comparator Floating-Point MultAdd, Add, Sub, Cvt, Div, Sqrt Multiplier Array
Joint TLB
DVA
Load Aligner
Coprocessor 0 System/Memory Control PC Incrementer
IVA
Adder StAln/Sh Logicals
FA Bus
Adder Shifter Logicals
Branch PC Adder ITLB Virtual Program Counter DTLB Virtual PLL/Clocks Int Mult, Div, Madd
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Integer Control
Integer Register File M Pipe F Pipe
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3
Description
PMC-Sierra's RM7000 is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit. To keep its multiple execution units running efficiently, the RM7000 integrates not only 16 KB 4-way set associative instruction and data caches but backs them up with an integrated 256 KB 4-way set associative secondary as well. For maximum efficiency, the data and secondary caches are write-back and non-blocking. An optional external tertiary cache provides high-performance capability even in applications having very large data sets. A RM5200 Family compatible, operating system friendlymemory management unit with a 64/48entry fully associative TLB and a high-performance 64-bit system interface supporting multiple outstanding reads with out-of-order return and hardware prioritized and vectored interrupts round out the main features of the processor. The RM7000 is ideally suited for high-end embedded control applications such as internetworking, high-performance image manipulation, high-speed printing, and 3-D visualization. The RM7000 is also applicable to the low end workstation market where its balanced integer and floating-point performance and direct support for a large tertiary cache (up to 8 MB) provide outstanding price/performance.
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4
Hardware Overview
The RM7000 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the RM7000 are briefly described below.
4.1
CPU Registers
Like all MIPS ISA processors, the RM7000 CPU has a simple, clean user visible state consisting of 32 general purpose registers (GPR), two special purpose registers for integer multiplication and division, and a program counter; there are no condition code bits. Figure 2 shows the user visible state.
Figure 2 CP0 Registers General Purpose Registers
63 0 r1 r2 * * * * r29 r30 r31 0
Multiply/Divide Registers
63 HI 63 LO 0 0
Program Counter
63 PC 0
4.2
Superscalar Dispatch
The RM7000 has an efficient symmetric superscalar dispatch unit which allows it to issue up to two instructions per cycle. For purposes of instruction issue, the RM7000 defines four classes of instructions: integer, load/store, branches, and floating-point. There are two logical pipelines, the function, or F, pipeline and the memory, or M, pipeline. Note however that the M pipe can execute integer as well as memory type instructions.
Table 1 Instruction Issue Rules F Pipe
one of: integer, branch, floating-point, integer mul, div
M Pipe
one of: integer, load/store
Figure 3 is a simplification of the pipeline section and illustrates the basics of the instruction issue mechanism.
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Figure 3
Instruction Issue Paradigm
Instruction Cache
Dispatch Unit F Pipe IBus M Pipe IBus
FP F Pipe
FP M Pipe
Integer F Pipe
Integer M Pipe
The figure illustrates that one F pipe instruction and one M pipe instruction can be issued concurrently but that two M pipe or two F pipe instructions cannot be issued. Table 2 specifies more completely the instructions within each class.
Table 2 Dual Issue Instruction Classes integer load/store floating-point
fadd, fsub, fmult, fmadd, fdiv, fcmp, fsqrt, etc.
branch
beq, bne, bCzT, bCzF, j, etc.
add, sub, or, xor, shift, lw, sw, ld, sd, ldc1, etc. sdc1, mov, movc, fmov, etc.
The symmetric superscalar capability of the RM7000, in combination with its low latency integer execution units and high-throughput fully pipelined floating-point execution unit, provides unparalleled price/performance in computational intensive embedded applications.
4.3
Pipeline
The logical length of both the F and M pipelines is five stages with state committing in the register write, or W, pipe stage. The physical length of the floating-point execution pipeline is actually seven stages but this is completely transparent to the user. Figure 4 shows instruction execution within the RM7000 when instructions are issuing simultaneously down both pipelines. As illustrated in the figure, up to ten instructions can be executing simultaneously. This figure presents a somewhat simplistic view of the processors operation however since the out-of-order completion of loads, stores, and long latency floatingpoint operations can result in there being even more instructions in process than what is shown.
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Figure 4 Pipeline
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 1I 1I 2I 2I 1R 1R 1I 1I 2R 2R 2I 2I 1A 1A 1R 1R 1I 1I 2A 2A 2R 2R 2I 2I 1D 1D 1A 1A 1R 1R 1I 1I 2D 2D 2A 2A 2R 2R 2I 2I 1W 1W 1D 1D 1A 1A 1R 1R 1I 1I 2W 2W 2D 2D 2A 2A 2R 2R 2I 2I 1W 1W 1D 1D 1A 1A 1R 1R 2W 2W 2D 2D 2A 2A 2R 2R 1W 1W 1D 1D 1A 1A 2W 2W 2D 2D 2A 2A 1W 1W 1D 1D 2W 2W 2D 2D 1W 1W 2W 2W
1I-1R: 2I: 2R: 1A: 1A: 1A-2A: 2A: 2A-2D: 1D: 2W:
one cycle Instruction cache access Instruction virtual to physical address translation Register file read, Bypass calculation, Instruction decode, Branch address calculation Issue or slip decision, Branch decision Data virtual address calculation Integer add, logical, shift Store Align Data cache access and load align Data virtual to physical address translation Register file write
Note that instruction dependencies, resource conflicts, and branches result in some of the instruction slots being occupied by NOPs.
4.4
Integer Unit
Like the RM5200 Fcamily, the RM7000 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors such as the R4650 and R4700 that implement the earlier generation MIPS III Instruction Set Architecture. Additionally, the RM7000 includes two implementation specific instructions not found in the baseline MIPS IV ISA, but that are useful in the embedded market place. Described in detail in a later section, these instructions are integer multiply-accumulate and three-operand integer multiply. The RM7000 integer unit includes thirty-two general purpose 64-bit registers, the HI/LO result registers for the two-operand integer multiply/divide operations, and the program counter, or PC. There are two separate execution units, one of which can execute function, or F, type instructions and one which can execute memory, or M, type instructions. See above for a description of the instruction types and the issue rules. As a special case, integer multiply/divide instructions as well as their corresponding MFHI and MFLO instructions can only be executed in the F type execution unit. Within each execution unit the operational characteristics are the same as on previous MIPS designs with single cycle ALU operations (add, sub, logical, shift), one cycle load delay, and an autonomous multiply/divide unit.
Register File
The RM7000 has thirty-two general purpose registers with register location 0 (r0) hard wired to a zero value. These registers are used for scalar integer operations and address calculation. In order to service the two integer execution units, the register file has four read ports and two write ports and is fully bypassed both within and between the two execution units to minimize operation latency in the pipeline.
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4.5
ALU
The RM7000 has two complete integer ALUs each consisting of an integer adder/subtractor, a logic unit, and a shifter. Table 3 shows the functions performed by the ALUs for each execution unit. Each of these units is optimized to perform all operations in a single processor cycle.
Table 3 Unit
Adder Logic Shifter
ALU Operations F Pipe
add, sub logic, moves, zero shifts (nop) non zero shift
M Pipe
add, sub, data address add logic, moves, zero shifts (nop) non zero shift, store align
4.6
Integer Multiply/Divide
The RM7000 has a single dedicated integer multiply/divide unit optimized for high-speed multiply and multiply-accumulate operations. The multiply/divide unit resides in the F type execution unit. Table 4 shows the performance of the multiply/divide unit on each operation.
Table 4 Integer Multiply/Divide Operations Opcode
MULT/U, MAD/U MUL DMULT, DMULTU DIV, DIVD DDIV, DDIVU
Operand Size
16 bit 32 bit 16 bit 32 bit any any any
Latency
4 5 4 5 9 36 68
Repeat Rate
3 4 3 4 8 36 68
Stall Cycles
0 0 2 3 0 0 0
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in the Hi and Lo registers. These values can then be transferred to the general purpose register file using the Move-from-Hi and Move-from-Lo (MFHI/MFLO) instructions. In addition to the baseline MIPS IV integer multiply instructions, the RM7000 also implements the 3-operand multiply instruction, MUL. This instruction specifies that the multiply result go directly to the integer register file rather than the Lo register. The portion of the multiply that would have normally gone into the Hi register is discarded. For applications where it is known that the upper half of the multiply result is not required, using the MUL instruction eliminates the necessity of executing an explicit MFLO instruction. Also included in the RM7000 are the multiply-add instructions MAD/MADU. This instruction multiplies two operands and adds the resulting product to the current contents of the Hi and Lo registers. The multiply-accumulate operation is the core primitive of almost all signal processing
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algorithms allowing the RM7000 to eliminate the need for a separate DSP engine in many embedded applications. By pipelining the multiply-accumulate function and dynamically determining the size of the input operands, the RM7000 is able to maximize throughput while still using an area efficient implementation.
4.7
Floating-Point Coprocessor
The RM7000 incorporates a high-performance fully pipelined floating-point coprocessor which includes a floating-point register file and autonomous execution units for multiply/add/convert and divide/square root. The floating-point coprocessor is a tightly coupled co-execution unit, decoding and executing instructions in parallel with, and in the case of floating-point loads and stores, in cooperation with the M pipe of the integer unit. As described earlier, the superscalar capabilities of the RM7000 allow floating-point computation instructions to issue concurrently with integer instructions.
4.8
Floating-Point Unit
The RM7000 floating-point execution unit supports single and double precision arithmetic, as specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root unit and a pipelined multiply/add unit. Overlap of divide/square root and multiply/add is supported. The RM7000 maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. Precise exceptions are extremely important in object-oriented programming environments and highly desirable for debugging in any environment. The floating-point unit's operation set includes floating-point add, subtract, multiply, multiplyadd, divide, square root, reciprocal, reciprocal square root, conditional moves, conversion between fixed-point and floating-point format, conversion between floating-point formats, and floatingpoint compare. Table 5 gives the latencies of the floating-point instructions in internal processor cycles.
4.9
Floating-Point General Register File
The floating-point general register file, FGR, is made up of thirty-two 64-bit registers. With the floating-point load and store double instructions, LDC1 and SDC1, the floating-point unit can take advantage of the 64-bit wide data cache and issue a floating-point coprocessor load or store doubleword instruction in every cycle. The floating-point control register file contains two registers; one for determining configuration and revision information for the coprocessor and one for control and status information. These registers are primarily used for diagnostic software, exception handling, state saving and restoring, and control of rounding modes.
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Table 5 Floating Point Latencies and Repeat Rates Operation
fadd fsub fmult fmadd fmsub fdiv fsqrt frecip frsqrt fcvt.s.d fcvt.s.w fcvt.s.l fcvt.d.s fcvt.d.w fcvt.d.l fcvt.w.s fcvt.w.d fcvt.l.s fcvt.l.d fcmp fmov, fmovc fabs, fneg
Latency Single/double
4 4 4/5 4/5 4/5 21/36 21/36 21/36 38/68 4 6 6 4 4 4 4 4 4 4 1 1 1
Repeat Rate Single/double
1 1 1/2 1/2 1/2 19/34 19/34 19/34 36/66 1 3 3 1 1 1 1 1 1 1 1 1 1
To support superscalar operations, the FGR has four read ports and two write ports, and is fully bypassed to minimize operation latency in the pipeline. Three of the read ports and one write port are used to support the combined multiply-add instruction while the fourth read and second write port allows a concurrent floating-point load or store and conditional moves.
4.10 System Control Coprocessor (CP0)
The system control coprocessor (CP0) in the MIPS architecture is responsible for the virtual memory sub-system, the exception control system, and the diagnostics capability of the processor. In the MIPS architecture, the system control coprocessor (and thus the kernel software) is implementation dependent. For memory management, the RM7000 CP0 is logically identical to that of the RM5200 Family and R5000. For interrupt exceptions and diagnostics, the RM7000 is a superset of the RM5200 Family and R5000 implementing additional features described later in the sections on Interrupts, the Test/Breakpoint facility, and the Performance Counter facility. The memory management unit controls the virtual memory system page mapping. It consists of an instruction address translation buffer (ITLB), a data address translation buffer (DTLB), a Joint TLB (JTLB), and coprocessor registers used by the virtual memory mapping sub-system.
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4.11 System Control Coprocessor Registers
The RM7000 incorporates all system control coprocessor (CP0) registers internally. These registers provide the path through which the virtual memory system's page mapping is examined and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). In addition, the RM7000 includes registers to implement a real-time cycle counting facility, to aid in cache and system diagnostics, and to assist in data error detection. To support the non-blocking caches and enhanced interrupt handling capabilities of the RM7000, both the data and control register spaces of CP0 are supported by the RM7000. In the data register space, that is the space accessed using the MFC0 and MTC0 instructions, the RM7000 supports the same registers as found in the RM5200, R4000 and R5000 families. In the control space, that is the space accessed by the previously unused CTC0 and CFC0 instructions, the RM7000 supports five new registers. The first three of these new 32-bit registers support the enhanced interrupt handling capabilities and are the Interrupt Control, Interrupt Priority Level Lo (IPLLO), and Interrupt Priority Level Hi (IPLHI) registers. These registers are described further in the section on interrupt handling. The other two registers, Imprecise Error 1 and Imprecise Error 2, have been added to help diagnose bus errors which occur on non-blocking memory references. Figure 5 shows the CP0 registers.
Figure 5 CP0 Registers
47 Info 7* Index 0* TLB Random 1* Wired 6* (entries protected from TLBWR) 0 LLAddr 17* TagLo 28* TagHi 29* PRId 15* Config 16* Watch2 19* ECC 26* XContext 20* CacheErr 27* ErrorEPC 30* Status 12* EPC 14* Cause 13* Watch1 18* Watch Mask 24*
Used for memory management
* Register number
Used for exception processing
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4.12 Virtual to Physical Address Mapping
The RM7000 provides three modes of virtual addressing: * * * user mode supervisor mode kernel mode
This mechanism is available to system software to provide a secure environment for user processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In the user mode, the RM7000 provides a single, uniform virtual address space of 256 GB (2 GB in 32bit mode). When operating in the kernel mode, four distinct virtual address spaces, totalling 1024 GB (4 GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address. The RM7000 processor also supports a supervisor mode in which the virtual address space is 256.5 GB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the virtual address. Figure 6 shows the address space layout for 32-bit operation.
Figure 6 Kernel Mode Virtual Addressing (32-bit mode)
Kernel virtual address space (kseg3) 0xE0000000 Mapped, 0.5GB Supervisor virtual address space (ksseg) 0xC0000000 Mapped, 0.5GB Uncached kernel physical address space (kseg1) 0xA0000000 Unmapped, 0.5GB Cached kernel physical address space (kseg0) 0x80000000 Unmapped, 0.5GB User virtual address space (kuseg) Mapped, 2.0GB
0xFFFFFFFF
0xDFFFFFFF
0xBFFFFFFF
0x9FFFFFFF
0x7FFFFFFF
When the RM7000 is configured for 64-bit addressing, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout.
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4.13 Joint TLB
For fast virtual-to-physical address translation, the RM7000 uses a large, fully associative TLB that maps virtual pages to their corresponding physical addresses. As indicated by its name, the joint TLB (JTLB) is used for both instruction and data translations. The JTLB is organized as pairs of even/odd entries, and maps a virtual address and address space identifier into the large, 64 GB physical address space. By default, the JTLB is configured as 48 pairs of even/odd entries. The 64 even/odd entry optional configuration is set at boot time. Two mechanisms are provided to assist in controlling the amount of mapped space, and the replacement characteristics of various memory regions. First, the page size can be configured, on a per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in 4X multiples). A CP0 register, PageMask, is loaded with the desired page size of a mapping, and that size is stored into the TLB along with the virtual address when a new entry is written. Thus, operating systems can create special purpose maps; for example, a typical frame buffer can be memory mapped using only one TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The RM7000 provides a random replacement algorithm to select a TLB entry to be written with a new mapping; however, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism allows the operating system to guarantee that certain pages are always mapped for performance reasons and for deadlock avoidance. This mechanism also facilitates the design of real-time systems by allowing deterministic access to critical software. The JTLB also contains information that controls the cache coherency protocol for each page. Specifically, each page has attribute bits to determine whether the coherency algorithm is: uncached, write-back, write-through with write-allocate, write-through without write-allocate, write-back with secondary and tertiary bypass. Note that both of the write-through protocols bypass both the secondary and the tertiary caches since neither of these caches support writes of less than a complete cache line. These protocols are used for both code and data on the RM7000 with data using write-back or write-through depending on the application. The write-through modes support the same efficient frame buffer handling as the RM5200 Family, R4700, and R5000.
4.14 Instruction TLB
The RM7000 uses a 4-entry instruction TLB (ITLB) to minimize contention for the JTLB, to eliminate the critical path of translating through a large associative array, and to save power. Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction address translation to occur in parallel with data address translation. When a miss occurs on an instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the JTLB. The operation of the ITLB is completely transparent to the user.
4.15 Data TLB
The RM7000 uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB. Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data address translation to occur in parallel with instruction address translation. When a miss occurs on a data
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address translation by the DTLB, the DTLB is filled from the JTLB. The DTLB refill is pseudoLRU: the least recently used entry of the least recently used pair of entries is filled. The operation of the DTLB is completely transparent to the user.
4.16 Cache Memory
In order to keep the RM7000's superscalar pipeline full and operating efficiently, the RM7000 has integrated primary instruction and data caches with single cycle access as well as a large unified secondary cache with a three cycle miss penalty from the primaries. Each primary cache has a 64bit read path, a 128-bit write path, and both caches can be accessed simultaneously. The primary caches provide the integer and floating-point units with an aggregate bandwidth of 4.8 GB per second at an internal clock frequency of 300 MHz. During an instruction or data primary cache refill, the secondary cache can provide a 64-bit datum every cycle following the initial three cycle latency for a peak bandwidth of 2.4 GB per second. For applications requiring even higher performance, the RM7000 also has a direct interface to a large external tertiary cache.
4.17 Instruction Cache
The RM7000 has an integrated 16 KB, four-way set associative instruction cache and, even though instruction address translation is done in parallel with the cache access, the combination of 4-way set associativity and 16 KB size results in a cache which is virtually indexed and physically tagged. Since the effective physical index eliminates the potential for virtual aliases in the cache, it is possible that some operating system code can be simplified vis-a-vis the RM5200 Family, R5000 and R4000 class processors. The data array portion of the instruction cache is 64 bits wide and protected by word parity while the tag array holds a 24-bit physical address, 14 housekeeping bits, a valid bit, and a single bit of parity protection. By accessing 64 bits per cycle, the instruction cache is able to supply two instructions per cycle to the superscalar dispatch unit. For signal processing, graphics, and other numerical code sequences where a floating-point load or store and a floating-point computation instruction are being issued together in a loop, the entire bandwidth available from the instruction cache will be consumed by instruction issue. For typical integer code mixes, where instruction dependencies and other resource constraints restrict the achievable parallelism, the extra instruction cache bandwidth is used to fetch both the taken and non-taken branch paths to minimize the overall penalty for branches. A 32-byte (eight instruction) line size is used to maximize the communication efficiency between the instruction cache and the secondary cache, tertiary cache, or memory system. The RM7000 is the first MIPS RISC microprocessor to support cache locking on a per line basis. The contents of each line of the cache can be locked by setting a bit in the Tag. Locking the line prevents its contents from being overwritten by a subsequent cache miss. Refill will occur only into unlocked cache lines. This mechanism allows the programmer to lock critical code into the cache thereby guaranteeing deterministic behavior for the locked code sequence.
4.18 Data Cache
The RM7000 has an integrated 16 KB, four-way set associative data cache, and even though data address translation is done in parallel with the cache access, the combination of 4-way set
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associativity and 16 KB size results in a cache which is physically indexed and physically tagged. Since the effective physical index eliminates the potential for virtual aliases in the cache, it is possible that some operating system code can be simplified vis-a-vis the RM5200 Family, R5000 and R4000 class processors. The data cache is non-blocking; that is, a miss in the data cache will not necessarily stall the processor pipeline. As long as no instruction is encountered which is dependent on the data reference which caused the miss, the pipeline will continue to advance. Once there are two cache misses outstanding, the processor will stall if it encounters another load or store instruction. A 32-byte (eight word) line size is used to maximize the communication efficiency between the data cache and the secondary cache, tertiary cache, or memory system. The data array portion of the data cache is 64 bits wide and protected by byte parity while the tag array holds a 24-bit physical address, three housekeeping bits, a two bit cache state field, and has two bits of parity protection. The normal write policy is write-back, which means that a store to a cache line does not immediately cause memory to be updated. This increases system performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. Software can, however, select write-through on a per-page basis when appropriate, such as for frame buffers. Cache protocols supported for the data cache are: 1. Uncached Reads to addresses in a memory area identified as uncached will not access the cache. Writes to such addresses will be written directly to main memory without updating the cache. 2. Write-back Loads and instruction fetches will first search the cache, reading the next memory hierarchy level only if the desired data is not cache resident. On data store operations, the cache is first searched to determine if the target address is cache resident. If it is resident, the cache contents will be updated, and the cache line marked for later write-back. If the cache lookup misses, the target line is first brought into the cache and then the write is performed as above. 3. Write-through with write allocate Loads and instruction fetches will first search the cache, reading from memory only if the desired data is not cache resident; write-through data is never cached in the secondary or tertiary caches. On data store operations, the cache is first searched to determine if the target address is cache resident. If it is resident, the primary cache contents will be updated and main memory will also be written leaving the write-back bit of the cache line unchanged; no writes will occur into the secondary or tertiary. If the cache lookup misses, the target line is first brought into the cache and then the write is performed as above. 4. Write-through without write allocate Loads and instruction fetches will first search the cache, reading from memory only if the desired data is not cache resident; write-through data is never cached in the secondary or tertiary caches. On data store operations, the cache is first searched to determine if the target address is cache resident. If it is resident, the cache contents will be updated and main memory will also be written leaving the write-back bit of the cache line unchanged; no writes will
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occur into the secondary or tertiary. If the cache lookup misses, then only main memory is written. 5. Fast Packet CacheTM (Write-back with secondary and tertiary bypass) Loads and instruction fetches first search the primary cache, reading from memory only if the desired data is not resident; the secondary and tertiary are not searched. On data store operations, the primary cache is first searched to determine if the target address is resident. If it is resident, the cache contents are updated, and the cache line marked for later write-back. If the cache lookup misses, the target line is first brought into the cache and then the write is performed as above. Associated with the Data Cache is the store buffer. When the RM7000 executes a STORE instruction, this single-entry buffer gets written with the store data while the tag comparison is performed. If the tag matches, then the data is written into the Data Cache in the next cycle that the Data Cache is not accessed (the next non-load cycle). The store buffer allows the RM7000 to execute a store every processor cycle and to perform back-to-back stores without penalty. In the event of a store immediately followed by a load to the same address, a combined merge and cache write will occur such that no penalty is incurred.
4.19 Secondary Cache
The RM7000 has an integrated 256 KB, four-way set associative, block write-back secondary cache. The secondary has the same line size as the primaries, 32 bytes, is logically 64-bits wide matching the system interface and primary widths, and is protected with doubleword parity. The secondary tag array holds a 20-bit physical address, two housekeeping bits, a three bit cache state field, and two parity bits. By integrating a secondary cache, the RM7000 is able to dramatically decrease the latency of a primary cache miss without dramatically increasing the number of pins and the amount of power required by the processor. From a technology point of view, integrating a secondary cache maximally leverages CMOS semiconductor technology by using silicon to build the structures that are most amenable to silicon technology; silicon is being used to build very dense, low power memory arrays rather than large power hungry I/O buffers. Further benefits of an integrated secondary are flexibility in the cache organization and management policies that are not practical with an external cache. Two previously mentioned examples are the 4-way associativity and write-back cache protocol. A third management policy for which integration affords flexibility is cache hierarchy management. With multiple levels of cache, it is necessary to specify a policy for dealing with cases where two cache lines at level n of the hierarchy would, if possible, be sharing an entry in level n+1 of the hierarchy. The policy followed by the RM7000 is motivated by the desire to get maximum cache utility and results in the RM7000 allowing entries in the primaries which do not necessarily have a corresponding entry in the secondary; the RM7000 does not force the primaries to be a subset of the secondary. For example, if primary cache line A is being filled and a cache line already exists in the secondary for primary cache line B at the location where primary A's line would reside then that secondary entry will be replaced by an entry corresponding to primary cache line A and no action will occur in the primary for cache line B. This operation will create the aforementioned scenario where the primary cache line which initially had a corresponding
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secondary entry will no longer have such an entry. Such a primary line is called an orphan. In general, cache lines at level n+1 of the hierarchy are called parents of level n's children. Another RM7000 cache management optimization occurs for the case of a secondary cache line replacement where the secondary line is dirty and has a corresponding dirty line in the primary. In this case, since it is permissible to leave the dirty line in the primary, it is not necessary to write the secondary line back to main memory. Taking this scenario one step further, a final optimization occurs when the aforementioned dirty primary line is replaced by another line and must be written back, in this case, it will be written directly to memory bypassing the secondary cache.
4.20 Secondary Caching Protocols
Unlike the primary data cache, the secondary cache supports only uncached and block write-back. As noted earlier, cache lines managed with either of the write-through protocols will not be placed in the secondary cache. A new caching attribute, write-back with secondary and tertiary bypass, allows the secondary, and the tertiary if present, to be bypassed entirely. When this attribute is selected, the secondary and tertiary will not be filled on load misses and will not be written on dirty write-backs from the primary.
4.21 Tertiary Cache
Like the RM5270, RM5271 and R5000, the RM7000 has direct support for an external cache. In the case of the RM527x chips this is a secondary cache whereas for the RM7000 this cache becomes a level-3, or tertiary cache. The tertiary cache is direct mapped and block write-through with byte parity protection for data. The RM7000 tertiary operates identical to the secondary of the RM527x and R5000 while supporting additional size increments to 4M and 8M byte caches. The tertiary interface uses the SysAD bus for data and tags while providing a separate bus, TcLine, for addresses, and a handful of tertiary specific control signals (for the complete set, see Pin Listing). A tertiary read looks nearly identical to a standard processor read except that the tag chip enable signal, TcTCE*, is asserted concurrently with ValidOut* and Release*, initiating a tag probe and indicating to the external controller that a tertiary cache access is being performed. As a result, the external controller monitors the tertiary hit signal, TcMatch, and if a hit is indicated the controller will abort the memory read and will refrain from acquiring control of the system interface. Along with TcTCE*, the processor also asserts the tag data enable signal, TcTDE*, which causes the tag RAMs to latch the SysAD address internally for use as the replacement tag if a cache miss occurs. On a tertiary miss, a refill is accomplished with a two signal handshake between the data output enable signal, TcDOE*, which is deasserted by the controller and the tag and data write enable signal, TcCWE*, which is asserted by the processor. Figure 7 illustrates a tertiary cache hit followed by a miss.
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Figure 7 Tertiary Cache Hit and Miss
Master SysClock SysAD TcLine[17:0] Addr Index I0 I1 I2 I3 Data0 Data1 Data2 Data3 Addr Index I0 I1 I2 I3 I0 I1 Data0 Data1 Data0 Data1 Processor Tertiary(Hit) Processor Tertiary(Miss) System
TcWord[1:0]
TcTCE* TcMatch TcDCE*
TcCWE*
TcDOE*
Other capabilities of the tertiary interface include block write, tag invalidate, and tag probe. For details of these transactions as well as detailed timing waveforms for all the tertiary transactions, see the R5000 or RM7000 Bus Interface Specifications. The tertiary cache tag can easily be implemented with standard components such as the Motorola MCM69T618. The RM7000 cache attributes for the instruction, data, internal secondary, and optional external tertiary caches are summarized in Table 6.
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Table 6 Cache Attributes Attribute
Size Associativity Replacement Algorithm. Line size Index Tag Write policy read policy read order write order miss restart following: Parity
Instruction
16KB 4-way cyclic 32 byte vAddr11..0 pAddr35..12 n.a. n.a. critical word first NA complete line per word
Data
16KB 4-way cyclic 32 byte vAddr11..0 pAddr35..12 write-back, writethrough non-blocking (2 outstanding) critical word first sequential first double (if waiting for data) per byte
Secondary
256KB 4-way cyclic 32 byte pAddr15..0 pAddr35..16 block write-back, bypass
Tertiary
512K, 1M, 2M, 4M, or 8M direct mapped direct replacement 32 byte pAddr22..0 pAddr35..19 block write-through, bypass
non-blocking (data non-blocking (data only, 2 outstanding) only, 2 outstanding) critical word first sequential n.a. per doubleword critical word first sequential n.a. per byte
4.22 Cache Locking
The RM7000 allows critical code or data fragments to be locked into the primary and secondary caches. The user has complete control over what locking is performed with cache line granularity. For instruction and data fragments in the primaries, locking is accomplished by setting either or both of the cache lock enable bits in the CP0 ECC register, specifying the set via a field in the CP0 ECC register, and then executing either a load instruction or a Fill_I cache operation for data or instructions respectively. Only two sets are lockable within each cache: set A and set B. Locking within the secondary works identically to the primaries using a separate secondary lock enable bit and the same set selection field. As with the primaries, only two sets are lockable: sets A and B. Table 7 summarizes the cache locking capabilities.
Table 7 Cache Locking Control Cache
Primary I Primary D Secondary
Lock Enable
ECC[27] ECC[26] ECC[25]
Set Select
ECC[28]=0A ECC[28]=1B ECC[28]=0A ECC[28]=1B ECC[28]=0A ECC[28]=1B
Activate
Fill_I Load/Store Fill_I or Load/Store
4.23 Cache Management
To improve the performance of critical data movement operations in the embedded environment, the RM7000 significantly improves the speed of operation of certain critical cache management
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operations vis-a-vis the R5000 and R4000 families. In particular, the speed of the Hit-WritebackInvalidate and Hit-Invalidate cache operations has been improved in some cases by an order of magnitude over that of the earlier families. Table 8 compares the RM7000 with the R4000 and R5000 processors.
Table 8 Penalty Cycles Penalty Operation
Hit-WritebackInvalidate
Condition RM7000
Miss Hit-Clean Hit-Dirty Miss Hit 0 3 3+n 0 2
R4000/R5000
7 12 14+n 7 9
Hit-Invalidate
For the Hit-Dirty case of Hit-Writeback-Invalidate, if the writeback buffer is full from some previous cache eviction then n is the number of cycles required to empty the writeback buffer. If the buffer is empty then n is zero. The penalty value is the number of processor cycles beyond the one cycle required to issue the instruction that is required to implement the operation.
4.24 Primary Write Buffer
Writes to secondary cache or external memory, whether cache miss write-backs or stores to uncached or write-through addresses, use the integrated primary write buffer. The write buffer holds up to four 64-bit address and data pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in parallel with memory update. For uncached and writethrough stores, the write buffer significantly increases performance by decoupling the SysAD bus transfers from the instruction execution stream.
4.25 System Interface
The RM7000 provides a high-performance 64-bit system interface which is compatible with the RM5200 Family and R5000. Unlike the R4000 and R5000 family processors which provide only an integral multiplication factor between SysClock and the pipeline clock, the RM7000 also allows half-integral multipliers, thereby providing greater granularity in the designers choice of pipeline and system interface frequencies. The interface consists of a 64-bit Address/Data bus with 8 check bits and a 9-bit command bus. In addition, there are ten handshake signals and ten interrupt inputs. The interface has a simple timing specification and is capable of transferring data between the processor and memory at a peak rate of 1000 MB/sec with a 125 MHz SysClock. Figure 8 shows a typical embedded system using the RM7000. This example shows a system with a bank of DRAMs, an optional tertiary cache, and an interface ASIC which provides DRAM control as well as an I/O port.
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Figure 8 Typical Embedded System Block Diagram
DRAM Flash/ Boot ROM Address Control x x
72 8
Latch
72
SysAD Bus
72 25
RM7000
SysCmd
72
Memory I/O Controller
PCI Bus
TcLine, etc.
Tertiary Cache (optional)
4.26 System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RM7000 and the rest of the system. It is protected with an 8-bit parity check bus, SysADC. The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies. The data rate and the bus frequency at which the RM7000 transmits data to the system interface are programmable via boot time mode control bits. Also, the rate at which the processor receives data is fully controlled by the external device. Therefore, either a low cost interface requiring no read or write buffering or a faster, high-performance interface can be designed to communicate with the RM7000. Again, the system designer has the flexibility to make these price/performance trade-offs.
4.27 System Command Bus
The RM7000 interface has a 9-bit System Command (SysCmd) bus. The command bus indicates whether the SysAD bus carries an address or data. If the SysAD bus carries an address, then the SysCmd bus also indicates what type of transaction is to take place (for example, a read or write). If the SysAD bus carries data, then the SysCmd bus also gives information about the data (for example, this is the last data word transmitted, or the data contains an error). The SysCmd bus is bidirectional to support both processor requests and external requests to the RM7000. Processor requests are initiated by the RM7000 and responded to by an external device. External requests are issued by an external device and require the RM7000 to respond. The RM7000 supports one to eight byte and 32-byte block transfers on the SysAD bus. In the case of a sub-doubleword transfer, the 3 low-order address bits give the byte address of the transfer, and the SysCmd bus indicates the number of bytes being transferred.
4.28 Handshake Signals
There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an external device to indicate to the RM7000 whether it can accept a new read or write
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transaction. The RM7000 samples these signals before deasserting the address on read and write requests. ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the processor to an external device. When an external device needs to control the interface, it asserts ExtRqst*. The RM7000 responds by asserting Release* to release the system interface to slave state. PRqst* and PAck* are used to transfer control of the SysAD and SysCmd buses from the external agent to the processor. These two pins are new to the interface relative to the RM52x, R4000 and R5000 families and have been added to support multiple outstanding reads and ultimately the nonblocking caches. When the processor needs to reacquire control of the interface, it asserts PRqst*. The external device responds by asserting PAck* to return control of the interface to the processor. RspSwap* is also a new pin and is used by the external agent to tell the processor when it is returning data out of order; i.e., when there are two outstanding reads, the external agent asserts RspSwap* when it is going to return the data for the second read before it returns the data for the first read. RspSwap* must be asserted by the external agent two cycles ahead of when it presents data so that the processor has time to switch to the correct address for writes into the tertiary cache. RdType is the last new pin on the interface. RdType indicates whether a read is an instruction read or a data read. When asserted the reference is an instruction read, when deasserted it is a data read. RdType is only valid during valid address cycles. ValidOut* and ValidIn* are used by the RM7000 and the external device respectively to indicate that there is a valid command or data on the SysAD and SysCmd buses. The RM7000 asserts ValidOut* when it is driving these buses with a valid command or data, and the external device drives ValidIn* when it has control of the buses and is driving a valid command or data.
4.29 System Interface Operation
Unlike the R4000 and R5000 processor families, to support the non-blocking caches and data Prefetch instructions, the RM7000 allows two outstanding reads. An external device may respond to read requests in whatever order it chooses by using the response order indicator pin RspSwap*. No more than two read requests will be submitted to the external device. Other than support for two outstanding reads, operation of the system interface is identical to that of the RM5270, RM5271 and R5000. Support for multiple outstanding reads can be enabled or disabled via a boottime mode bit. The RM7000 can issue read and write requests to an external device, while an external device can issue null and write requests to the RM7000. For processor reads, the RM7000 asserts ValidOut* and simultaneously drives the address and read command on the SysAD and SysCmd buses. If the system interface has RdRdy* asserted, then the processor tristates its drivers and releases the system interface to slave state by asserting Release*. The external device can then begin sending data to the RM7000. Figure 9 shows a processor block read request and the external agent read response for a system with either no tertiary cache or a transaction where the tertiary is being bypassed.
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Figure 9 Processor Block Read
SysClock SysAD SysCmd ValidOut* ValidIn*
Addr Read
Data0
Data1 NData
Data2 NData
Data3 NEOD
NData
RdRdy* WrRdy* Release*
The read latency is four cycles (ValidOut* to ValidIn*), and the response data pattern is DDxxDD. Figure 10 shows a processor block write where the processor was programmed with write-back data rate boot code 2, or DDxxDDxx. Finally, Figure 11 shows a typical sequence resulting in two outstanding reads both with initial tertiary cache accesses, as explained in the following sequence. 1. The processor issues a read which misses in the tertiary cache. 2. The external agent takes control of the bus in preparation for returning data to the processor. 3. The processor encounters another internal cache miss and therefore asserts PRqst* in order to regain control of the bus. 4. The external agent pulses PAck*, returning control of the bus to the processor. 5. The processor issues a read for the second miss.
6. The second cycle also misses in the tertiary. 7. The RspSwap* pin is asserted to denote the out of order response. Not shown in the figure is the completion of the data transfer for the second miss, or any of the data transfer for the first miss. 8. The external agent retakes control of the bus and begins returning data (out of order) for the second miss to the processor.
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Figure 10 Processor Block Write
SysClock Addr Write Data0 NData Data1 NData Data2 NData Data3 NEOD
SysAD SysCmd ValidOut* ValidIn*
RdRdy* WrRdy*
Release*
Figure 11 Multiple Outstanding Reads
Master SysClock SysAD SysCmd RspSwap* ValidOut* ValidIn* Addr1 Read1 Data0 Data1 Addr2 Read2 Data0 Data1 Data02 NData Data12 NData Processor Tertiary(Miss) System Processor Tertiary(Miss) System
2
5
7
8
Release* PRqst*
3 4 1 6
PAck* TcMatch
4.30 Data Prefetch
The RM7000 is the first PMC-Sierra design to support the MIPS IV integer data prefetch (PREF) and floating-point data prefetch (PREFX) instructions. These instructions are used by the compiler or by an assembly language programmer when it is known or suspected that an upcoming data reference is going to miss in the cache. By appropriately placing a prefetch instruction, the memory latency can be hidden under the execution of other instructions. If the execution of a prefetch instruction would cause a memory management or address error exception the prefetch is treated as a NOP.
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The "Hint" field of the data prefetch instruction is used to specify the action taken by the instruction. The instruction can operate normally (that is, fetching data as if for a load operation) or it can allocate and fill a cache line with zeroes on a primary data cache miss.
4.31 Enhanced Write Modes
Like previous MIPS processor designs, the RM7000 implements two enhancements to the original R4000 write mechanism: Write Reissue and Pipeline Writes. In write reissue mode, a write rate of one write every two bus cycles can be achieved. A write issues if WrRdy* is asserted two cycles earlier and is still asserted during the issue cycle. If it is not still asserted then the last write will reissue. Pipelined writes have the same two bus cycle write repeat rate, but can issue one additional write following the deassertion of WrRdy*.
4.32 External Requests
The RM7000 can respond to certain requests issued by an external device. These requests take one of two forms: Write requests and Null requests. An external device executes a write request when it wishes to update one of the processors writable resources such as the internal interrupt register. A null request is executed when the external device wishes the processor to reassert ownership of the processor external interface. Typically a null request will be executed after an external device, that has acquired control of the processor interface via ExtRqst*, has completed an independent transaction between itself and system memory in a system where memory is connected directly to the SysAD bus. Normally this transaction would be a DMA read or write from the I/O system.
4.33 Test/Breakpoint Registers
To increase both observability and controllability of the processor thereby easing hardware and software debugging, a pair of Test/Break-point, or Watch, registers, Watch1 and Watch2, have been added to the RM7000. Each Watch register can be separately enabled to watch for a load address, a store address, or an instruction address. All address comparisons are done on physical addresses. An associated register, Watch Mask, has also been added so that either or both of the Watch registers can compare against an address range rather than a specific address. The range granularity is limited to a power of two. When enabled, a match of either Watch register results in an exception. If the Watch is enabled for a load or store address then the exception is the Watch exception as defined for the R4000 with Cause exception code twenty-three. If the Watch is enabled for instruction addresses then a newly defined Instruction Watch exception is taken and the Cause code is sixteen. The Watch register which caused the exception is indicated by Cause bits 25..24. Table 9 summarizes a Watch operation.
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Table 9 Watch Control Register Register
Watch1, 2
Bit Field/Function
63 Store 31:2 62 Load 61 Instr 60:36 0 35:2 Addr 1 1:0 0 0
Watch Mask Mask
Mask Mask Watch Watch 2 1
4.34 Performance Counters
Like the Test/Break-point capability described above, the Performance Counter feature has been added to improve the observability and controllability of the processor thereby easing system debug and, especially in the case of the performance counters, easing system tuning. The Performance Counter feature is implemented using two new CP0 registers, PerfCount and PerfControl. The PerfCount register is a 32-bit writable counter which causes an interrupt when bit 31 is set. The PerfControl register is a 32-bit register containing a five bit field which selects one of twenty-two event types as well as a handful of bits which control the overall counting function. Note that only one event type can be counted at a time and that counting can occur for user code, kernel code, or both. The event types and control bits are listed in Table 10.
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Table 10 Performance Counter Control PerfControl Field
4..0
Description
Event Type 00: 01: 02: 03: 04: 05: 06: 07: 08: 09: 0A: 0B: 0C: 0D: 0E: 0F: 10: 11: 12: 13: 14: 15: 16: 17: 18: 19: 1A: 1B: 1C: 1D: 1E: Clock cycles Total instructions issued Floating-point instructions issued Integer instructions issued Load instructions issued Store instructions issued Dual issued pairs Branch prefetches External Cache Misses Stall cycles Secondary cache misses Instruction cache misses Data cache misses Data TLB misses Instruction TLB misses Joint TLB instruction misses Joint TLB data misses Branches taken Branches issued Secondary cache writebacks Primary cache writebacks Dcache miss stall cycles (cycles where both cache miss tokens taken and a third address is requested) Cache misses FP possible exception cycles Slip Cycles due to multiplier busy Coprocessor 0 slip cycles Slip cycles doe to pending non-blocking loads Write buffer full stall cycles Cache instruction stall cycles Multiplier stall cycles Stall cycles due to pending non-blocking loads - stall start of exception
7..5 8
Reserved (must be zero) Count in Kernel Mode 0: 1: Disable Enable
9
Count in User Mode 0: 1: Disable Enable
10
Count Enable 0: 1: Disable Enable
31..11
Reserved (must be zero)
The performance counter interrupt will only occur when interrupts are enabled in the Status register, IE=1, and Interrupt Mask bit 13 (IM[13]) of the coprocessor 0 interrupt control register is not set.
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Since the performance counter can be set up to count clock cycles, it can be used as either a) a second timer or b) a watchdog interrupt. A watchdog interrupt can be used as an aid in debugging system or software "hangs." Typically the software is setup to periodically update the count so that no interrupt will occur. When a hang occurs the interrupt ultimately triggers thereby breaking free from the hang-up.
4.35 Interrupt Handling
In order to provide better real time interrupt handling, the RM7000 provides an extended set of hardware interrupts each of which can be separately prioritized and separately vectored. In addition to the six external interrupt pins available on the R4000 and R5000 family processors, the RM7000 provides four more interrupt pins for a total of ten external interrupts. As described above, the performance counter is also a hardware interrupt source, INT[13]. Also, whereas the R4000 and R5000 family processors map the timer interrupt onto INT[7], the RM7000 provides a separate interrupt, INT[12], for this purpose freeing INT[7] for use as a pure external interrupt. All of these interrupts, INT[13..0], the Performance Counter, and the Timer, have corresponding interrupt mask bits, IM[13..0], and interrupt pending bits, IP[13..0], in the Status, Interrupt Control, and Cause registers. The bit assignments for the Interrupt Control and Cause registers are shown in Table 11 and Table 12. The Status register has not changed from the RM5200 Family and R5000, and is not shown. The IV bit in the Cause register is the global enable bit for the enhanced interrupt features. If this bit is clear then interrupt operation is compatible with the RM5200 Family and R5000. Although not related to the interrupt mechanism, note that the W1 and W2 bits indicate which Watch register caused a particular Watch exception. In the Interrupt Control register, the interrupt vector spacing is controlled by the Spacing field as described below. The Interrupt Mask field (IM[15..8]) contains the interrupt mask for interrupts eight through thirteen. IM[15..14] are reserved for future use. The Timer Exclusive (TE) bit if set moves the Timer interrupt to INT[12]. If clear, the Timer interrupt will be or'ed into INT[7] as on the R5000. The Interrupt Control register uses IM13 to enable the Performance Counter Control. Priority of the interrupts is set via two new coprocessor 0 registers called Interrupt Priority Level Lo (IPLLO) and Interrupt Priority Level Hi (IPLHI).
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Table 11 Cause Register 31
BD
30
0
29,28
CE
27
0
26
W2
25
W1
24
IV
23..8
IP[15..0]
7
0
6..2
EXC
0,1
0
Table 12 Interrupt Control Register 31..16
0
15..8
7
6..5
0
4..0
Spacing
IM[15..8] TE
Table 13 IPLLO Register 31..28
IPL7
27..24
IPL6
23..20
IPL5
19..16
IPL4
15..12
IPL3
11..8
IPL2
7..4
IPL1
3..0
IPL0
Table 14 IPLHI Register 31..28
0
27..24
0
23..20
IPL13
19..16
IPL12
15..12
IPL11
11..8
IPL10
7..4
IPL9
3..0
IPL8
These two registers contain a four-bit field corresponding to each interrupt thereby allowing each interrupt to be programmed with a priority level from 0 to 13 inclusive. The priorities can be set in any manner including having all the priorities set exactly the same. Priority 0 is the highest level and priority 15 the lowest. The format of the priority level registers is shown in Table 13 and Table 14 above. The priority level registers are located in the coprocessor 0 control register space. For further details about the control space see the section describing coprocessor 0. In addition to programmable priority levels, the RM7000 also permits the spacing between interrupt vectors to be programmed. For example, the minimum spacing between two adjacent vectors is 0x20 while the maximum is 0x200. This programmability allows the user to either set up the vectors as jumps to the actual interrupt routines or, if interrupt latency is paramount, to include the entire interrupt routine at the vector. Table 15 illustrates the complete set of vector spacing selections along with the coding as required in the Interrupt Control register bits 4:0. In general, the active interrupt priority combined with the spacing setting generates a vector offset which is then added to the interrupt base address of 0x200 to generate the interrupt exception offset. This offset is then added to the exception base to produce the final interrupt vector address.
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Table 15 Interrupt Vector Spacing ICR[4..0]
0x0 0x1 0x2 0x4 0x8 0x10 others
Spacing
0x000 0x020 0x040 0x080 0x100 0x200 reserved
4.36 Standby Mode
The RM7000 provides a means to reduce the amount of power consumed by the internal core when the CPU would not otherwise be performing any useful operations. This state is known as Standby Mode. Executing the WAIT instruction enables interrupts and enters Standby Mode. When the WAIT instruction completes the W pipe stage, if the SysAD bus is currently idle, the internal processor clocks will stop thereby freezing the pipeline. The phase lock loop, or PLL, internal timer/counter, and the "wake up" input pins: INT[9:0]*, NMI*, ExtReq*, Reset*, and ColdReset* continue to operate in their normal fashion. If the SysAD bus is not idle when the WAIT instruction completes the W pipe stage, then the WAIT is treated as a NOP. Once the processor is in Standby, any interrupt, including the internally generated timer interrupt, will cause the processor to exit Standby and resume operation where it left off. The WAIT instruction is typically inserted in the idle loop of the operating system or real time executive.
4.37 JTAG Interface
The RM7000 interface supports JTAG boundary scan in conformance with IEEE 1149.1. The JTAG interface is especially helpful for checking the integrity of the processor's pin connections.
4.38 Boot-Time Options
Fundamental operational modes for the processor are initialized by the boot-time mode control interface. The boot-time mode control interface is a serial interface operating at a very low frequency (SysClock divided by 256). The low frequency operation allows the initialization information to be kept in a low cost EPROM; alternatively the twenty or so bits could be generated by the system interface ASIC. Immediately after the VccOK signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all the fundamental operational modes. ModeClock runs continuously from the assertion of VccOK.
4.39 Boot-Time Modes
The boot-time serial mode stream is defined in Table 16. Bit 0 is the bit presented to the processor when VccOK is de-asserted; bit 255 is the last.
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Table 16 Boot Time Mode Stream
Mode bit
0 4..1
Description
reserved (must be zero) Write-back data rate 0: 1: 2: 3: 4: 5: 6: 7: 8: 9-15: DDDD DDxDDx DDxxDDxx DxDxDxDx DDxxxDDxxx DDxxxxDDxxxx DxxDxxDxxDxx DDxxxxxxDDxxxxxx DxxxDxxxDxxxDxxx reserved
Mode bit
17..16 19..18
Description
System configuration identifiers - software visible in processor Config[21..20] register Reserved: Must be zero
7..5
SysClock to Pclock Multiplier Mode bit 20 = 0 / Mode bit 20 = 1 0: 1: 2: 3: 4: 5: 6: 7: Multiply by 2/x Multiply by 3/x Multiply by 4/x Multiply by 5/2.5 Multiply by 6/x Multiply by 7/3.5 Multiply by 8/x Multiply by 9/4.5
20
Pclock to SysClock multipliers. 0: 1: Integer multipliers (2,3,4,5,6,7,8,9) Half integer multipliers (2.5,3.5,4.5)
8
Specifies byte ordering. Logically ORed with BigEndian input signal. 0: 1: Little endian Big endian
23..21
Reserved: Must be zero
10..9
Non-Block Write Control 00: 01: 10: 11: R4000 compatible non-block writes reserved pipelined non-block writes non-block write re-issue
24
JTLB Size. 0: 1: 48 dual-entry 64 dual-entry
11
Timer Interrupt Enable/Disable 0: 1: Enable the timer interrupt on IP[5] Disable the timer interrupt on IP[5]
25
On-chip secondary cache control. 0: 1: Disable Enable
12
Enable the external tertiary cache 0: 1: Disable Enable
26
Enable two outstanding reads with out-of-order return 0: 1: Disable Enable
14..13
Output driver strength - 100% = fastest 00: 01: 10: 11: 67% strength 50% strength 100% strength 83% strength
255..27
Reserved: Must be zero
15
External Tertiary cache RAM type: 0: 1: Dual-cycle deselect (DCD) Single-cycle deselect (SCD)
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Pin Descriptions
The following is a list of control, data, clock, tertiary cache, interrupt, and miscellaneous pins of the RM7000.
Table 17 System interface Pins Pin Name
ExtRqst* Release*
Type
Input Output
Description
External request Signals that the system interface is submitting an external request. Release interface Signals that the processor is releasing the system interface to slave state Read Ready Signals that an external agent can now accept a processor read. Write Ready Signals that an external agent can now accept a processor write request. Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. Processor Request When asserted this signal requests that control of the system interface be returned to the processor. This is enabled by Mode Bit 26. Processor Acknowledge When asserted, in response to PRqst*, this signal indicates to the processor that it has been granted control of the system interface. Response Swap RspSwap* is used by the external agent to signal the processor when it is about to return a memory reference out of order; i.e., of two outstanding memory references, the data for the second reference is being returned ahead of the data for the first reference. In order that the processor will have time to switch the address to the tertiary cache, this signal must be asserted a minimum of two cycles prior to the data itself being presented. Note that this signal works as a toggle; i.e., for each cycle that it is held asserted the order of return is reversed. By default, anytime the processor issues a second read it is assumed that the reads will be returned in order; i.e., no action is required if the reads are indeed returned in order. This is enabled by Mode Bit 26. Read Type During the address cycle of a read request, RdType indicates whether the read request is an instruction read or a data read. System address/data bus A 64-bit address and data bus for communication between the processor and an external agent.
RdRdy* WrRdy*
Input Input
ValidIn*
Input
ValidOut*
Output
PRqst*
Output
PAck*
Input
RspSwap*
Input
RdType
Output
SysAD(63:0)
Input/Output
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Pin Name
SysADC(7:0)
Type
Input/Output
Description
System address/data check bus An 8-bit bus containing parity check bits for the SysAD bus during data cycles. System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. System Command/Data Identifier Bus Parity For the RM7000, unused on input and zero on output.
SysCmd(8:0)
Input/Output
SysCmdP
Input/Output
Table 18 Clock/control interface Pins Pin Name
SysClock
Type
Input
Description
System clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization Vcc for PLL Quiet VccInt for the internal phase locked loop. Must be connected to VccInt through a filter circuit. Vss for PLL Quiet Vss for the internal phase locked loop. Must be connected to VssInt through a filter circuit.
VccP
Input
VssP
Input
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Table 19 Tertiary cache interfacePins Pin Name
TcCLR*
Type
Output
Description
Tertiary Cache Block Clear Requests that all valid bits be cleared in the Tag RAMs. Many RAM's may not support a block clear therefore the block clear capability is not required for the cache to operate. Tertiary Cache Write Enable Asserted to cause a write to the cache. Two identical signals are provided to balance the capacitive load relative to the remaining cache interface signals. Tertiary Cache Data RAM Chip Enable When asserted this signal causes the data RAM's to read out their contents. Two identical signals are provided to balance the capacitive load relative to the remaining cache interface signals Tertiary Cache Data RAM Output Enable When asserted this signal causes the data RAM's to drive data onto their I/O pins. This signal is monitored by the processor to determine when to drive the data RAM write enable in a tertiary cache miss refill sequence. Tertiary Cache Line Index Tertiary Cache Tag Match This signal is asserted by the cache Tag RAM's when a match occurs between the value on its data inputs and the contents of the addressed location in the RAM. Tertiary Cache Tag RAM Chip Enable When asserted this signal will cause either a probe or a write of the Tag RAM's depending on the state of the Tag RAM's write enable signal. This signal is monitored by the external agent and indicates to it that a tertiary cache access is occurring. Tertiary Cache Tag RAM Data Enable When asserted this signal causes the value on the data inputs of the Tag RAM to be latched into the RAM. If a refill of the RAM is necessary, this latched value will be written into the Tag RAM array. Latching the Tag allows a shared address/data bus to be used without incurring a penalty to re-present the Tag during the refill sequence. Tertiary Cache Tag RAM Output Enable When asserted this signal causes the Tag RAM's to drive data onto their I/O pins. Tertiary Cache Double Word Index Driven by the processor on cache hits and by the external agent on cache miss refills. Tertiary Cache Valid This signal is driven by the processor as appropriate to make a cache line valid or invalid. On Tag read operations the Tag RAM will drive this signal to indicate the line state.
TcCWE*(1:0)
Output
TcDCE*(1:0)
Output
TcDOE*
Input
TcLine(17:0) TcMatch
Output Input
TcTCE*
Output
TcTDE*
Output
TcTOE*
Output
TcWord(1:0)
Input/Output
TcValid
Input/Output
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Table 20 Interrupt Interface Pins Pin Name
Int*(9:0)
Type
Input
Description
Interrupt Ten general processor interrupts, bit-wise ORed with bits 9:0 of the interrupt register. Non-maskable interrupt Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 6 in R5000 compatibility mode).
NMI*
Input
Table 21 JTAG Interface Pins Pin Name
JTDI JTCK JTDO JTMS
Type
Input Input Output Input
Description
JTAG data in JTAG serial data in. JTAG clock input JTAG serial clock input. JTAG data out JTAG serial data out. JTAG command JTAG command signal, signals that the incoming serial data is command data.
Table 22 Initialization Interface Pins Pin Name
BigEndian
Type
Input
Description
Big Endian / Little Endian Control Allows the system to change the processor addressing mode without rewriting the mode ROM. Vcc is OK When asserted, this signal indicates to the RM7000 that the 2.5V power supply has been above 2.25V for more than 100 milliseconds and will remain stable. The assertion of VccOK initiates the reading of the boot-time mode control serial stream. Cold Reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with SysClock. Reset This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with SysClock. Boot Mode Clock Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six. Boot Mode Data In Serial boot-mode data input.
VccOK
Input
ColdReset*
Input
Reset*
Input
ModeClock
Output
ModeIn
Input
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Absolute Maximum Ratings1
Symbol
VTERM TCASE TSTG IIN IOUT
Rating
Terminal Voltage with respect to VSS Operating Temperature Storage Temperature DC Input Current3 DC Output Current4
Limits
-0.52 to +3.9 0 to +85 -55 to +125 20 20
Unit
V C C mA mA
Notes 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VIN minimum = -2.0 V for pulse width less than 15 ns. VIN should not exceed 3.9 Volts. 3. When VIN < 0V or VIN > VccIO 4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
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Recommended Operating Conditions
CPU Speed
200 - 250 MHz 266 MHz 300 MHz
Temperature
0C to +85C (Case) 0C to +85C (Case) 0C to +70C (Case)
Vss
0V 0V 0V
VccInt
2.5V 5% 2.5V 3% 2.6V .05V
VccIO
3.3V 5% 3.3V 5% 3.3V 5%
VccP
2.5V 5% 2.5V 3% 2.6V .05V
Notes 1. VCC I/O should not exceed VccInt by greater than 1.2 V during the power-up sequence. 2. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended. 3. As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. Refer to the RM7000 Family Users Manual, Appendix E. 4. VccP must be connected to VccInt through a passive filter circuit. See RM7000 Family User's Manual for recommended circuit.
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DC Electrical Characteristics
Parameter VOL VOH VOL VOH VIL VIH IIN 2.4V -0.3V 2.0V 0.8V VccIO + 0.3V 15 A 15 A VIN = 0 VIN = VccIO VccIO - 0.2V 0.4V |IOUT| = 2 mA
Minimum
Maximum
0.2V
Conditions |IOUT|= 100 A
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Power Consumption
CPU Clock Speed 200 MHz Parameter
VccInt standb Power (mWatt active s)
250 MHz Typ1 Max
1000
266 MHz Typ1 Max
1500
300 MHz Typ1 Max
2000
Conditions
No SysAD bus activity R4000 write protocol with no FPU operation (integer instructions only) Write re-issue or pipelined writes with superscalar (Integer and floating point instructions)
Typ1
Max
500
2200 4400 2700 5400 2800 5600 3800 7600
2550 5100 3150 6300 3300 6600 4250 8500
Notes 1. Typical integer instruction mix and cache miss rates with worst case supply voltage. 2. Worst case instruction mix with worst case supply voltage. 3. I/O supply power is application dependant, but typically <10% of VccInt.
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AC Electrical Characteristics
Parameter
Load Derate
10.1 Capacitive Load Deration
Symbol
CLD
Min
Max
2
Units
ns/25pF
10.2 Clock Parameters
CPU Speed Test Parameter
SysClock High SysClock Low SysClock Frequency7 SysClock Period tSCP Clock Jitter for SysClock SysClock Rise Time SysClock Fall Time ModeClock Period JTAG Clock Period tJitterIn tSCRise tSCFall tModeCKP tJTAGCKP 4
200 MHz Min
250 MHz
3 3
266 MHz
3 3
300 MHz Max Units
ns ns 120 30 MHz ns 3 3
Symbol Conditions
tSCHigh tSCLow
Max Min
Max Min
Max Min
Transition 5ns 3 Transition 5ns 3 25 100 40 200 2 2 256
25
125 40 150 2 2 256
33.3
105 30 150 2 2 256
33.3
150 ps 2 2 256 4 ns ns tSCP tSCP
4
4
Note:
Operation of the RM7000 is only guaranteed with the Phase Lock Loop Enabled.
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10.3 System Interface Parameters
CPU Speed 200 MHz Parameter
Data Output
1
250 MHz
1.0 1.0 1.0 1.0 2.5 1.0 5.0 5.5 6.0 6.5
266 MHz
1.0 1.0 1.0 1.0 2.5 1.0 4.5 5.0 5.0 6.0
300 MHz Max Units
4.5 4.5 5.0 5.5 ns ns ns ns ns ns 1.0 1.0 1.0 1.0 2.5 1.0
Symbol Test Conditions
tDO mode14..13 = 11 mode14..13 = 00 mode14..13 = 01 (slowest)
Min Max Min
5.0 5.5 6.0 7.0 1.0 1.0 1.0 2.5 1.0
Max Min
Max Min
2,3
mode14..13 = 10 (fastest) 1.0
Data Setup4 Data Hold4
tDS tDH
trise = see above table tfall = see above table
Notes 1. Timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O. 2. Capacitive load for all output timings is 50 pF. 3. Data Output timing applies to all signal pins whether tristate I/O or output only. 4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only. 5. Only mode 14:13 = 10 is tested and guaranteed.
10.4 Boot-Time Interface Parameters
Parameter7
Mode Data Setup
Symbol
tDS
Test Conditions
Min
4 0
Max
Units
SysClock cycles SysClock cycles
Mode Data Hold tDH
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Timing Diagrams
Figure 12 Clock Timing
SysClock tRise tFall tHigh tLow tJitterIn
11.1 Clock Timing
System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.)
Figure 13 Input Timing
SysClock tDS Data Data tDH
Figure 14
Output Timing
SysClock tDOmax Data tDOmin Data Data
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Packaging Information
304 TBGA Drawing
1.27 mm 1.27 mm OO A1 ball corner ink mark D
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G H J K L M N P R T U V W Y AA AB AC
E
E1, N
e
DETAIL B TOP VIEW D1, M
e
BOTTOM VIEW
SIDE VIEW
DETAIL A b
A
A2 f P DETAIL B
A1 DETAIL A
aaa
Body Size: 31.0 x 31.0 mm Package
Symbol A A1 A2 D, E D1, E1 M,N M1 b e aaa bbb f P Theta JC Theta JA Min 1.45 0.60 0.85 30.80 27.94 23 x 23 4 0.65 1.27 0.15 0.15 0.30 0.25 0.3 13 0.35 0.40 0.75 0.85 Nominal 1.55 0.65 0.90 31.00 Max 1.65 0.70 0.95 31.20 Note Overall Thickness Ball Height Body Thickness Body Size Ball Footprint Ball Matrix Number of Rows Deep Ball Diameter Ball Pitch Coplanarity Parallel Seating Plan Clearance Encapsulation Height Deg. C/Watt Deg. C/Watt @ 0 cfm air flow.
Note: All dimensions in millimeters unless otherwise indicated.
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RM7000 Pinout
Pin
A1 A5 A9 A13 A17 A21 B2 B6 B10 B14 B18 B22 C3 C7 C11 C15 C19 C23 D4 D8 D12 D16 D20 E1 E20 F1 F20 G1 G20 H1 H20 J1 J20 K1 K20 L1 L20 M1
Function
VccIO Do not connect SysAD[32] Vcclnt SysAD[61] VsslO VcclO SysAD[35} SysADC[5] SysADC[6] SysAD[28] VcclO VcclO SysAD[3] SysADC[4] SysAD[62] VsslO VcclO Vcclnt VcclO Vcclnt VcclO Vcclnt VcclO VsslO VcclO SysAD[36] TcLine[2] VsslO Vcclnt SysAD[7] VcclO SysAD[40] SysAD[25] SysAD[10] Vcclnt VsslO
Pin
A2 A6 A10 A14 A18 A22 B3 B7 B11 B15 B19 B23 C4 C8 C12 C16 D1 D5 D9 D13 D17 D21 E2 E21 F2 F21 G2 G21 H2 H21 J2 J21 K2 K21 L2 L21 M2
Function
VssIO VsslO SysADC[1] Vcclnt VsslO VsslO Vsslnt SysAD[34] SysADC[0] TcLine[5] VsslO VcclO SysAD[2] Vcclnt Vcclnt VcclO TcLine[13] VcclO VcclO Vcclnt TcLine[7] VcclO TcLine[14] TcLine[16] TcLine[3] SysAD[4] Vcclnt SysAD[37] SysAD[27] SysAD[6] Vccint SysAD[8] SysAD[24] SysAD[41] SysAD[54] SysAD[11]
Pin
A3 A7 A11 A15 A19 A23 B4 B8 B12 B20 C1 C5 C9 C13 C17 C21 D2 D6 D10 D14 D18 D22 E3 F3 F22 G3 G22 H3 H22 J3 J22 K3 K22 L3 L22 M3
Function
VssIO
Pin
A4
Function
TcLine[11] VsslO VsslO VsslO TcLine[4] Vsslnt TcLine[10] SysAD[33] SysADC[7] SysAD[29] Vsslnt Vsslnt TcLine[9] SysAD[0] SysADC[2] TcLine[6] Vsslnt VcclO TcLine[8] Vcclnt VcclO VcclO Do Not Connect VcclO TcLine[1] VcclO VsslO Vcclnt SysAD[58] Do Not Connect VsslO VcclO SysAD[56] SysAD[38] SysAD[23] Vcclnt SysAD[53] VcclO
Do Not Connect A8 Do Not Connect A12 SysAD[63] VcclO VsslO Vcclnt SysAD[30] VsslO VsslO Vcclnt SysADC[3] SysAD[60] VcclO VsslO VcclO SysAD[1] SysAD[31] VcclO VsslO TcLine[12] TcLine[15] TcLine[0] TcLine[17] SysAD[59] SysAD[5] SysAD[26] Vcclnt SysAD[57] SysAD[39] SysAD[55] SysAD[9] SysAD[22] SysAD[42] A16 B1 B5 B9 B17 B21 C2 C10 C14 C18 C22 D3 D7 D11 D15 D19 D23 E4 F4 F23 G4 G23 H4 H23 J4 J23 K4 K23 L4 L23 M4 Do Not Connect A20
Do Not Connect B13
Do Not Connect B16
Do Not Connect C6
Do Not Connect C20
Do Not Connect E22
Do Not Connect E23
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use Document ID: PMC-2002175, Issue 1
51
RM7000TM Microprocessor with On-Chip Secondary Cache Datasheet Released
Pin
M20 N1 N20 P1 P20 R1 R20 T1 T20 U1 U20 V1 V20 W1 W20 Y1 Y5 Y9 Y13 Y17 Y21 AA2 AA6
Function
VcclO SysAD[43] SysAD[19] SysAD[13] Vcclnt SysAD[46] VcclO VsslO ExtRqst* PAck* Vcclnt VsslO VcclO JTDI VcclO VcclO VcclO SysCmd[5] INT[2]* VcclO Vsslnt TcMatch
Pin
M21 N2 N21 P2 P21 R2 R21 T2 T21 U2 U21 V2 V21 W2 W21 Y6 Y10 Y14 Y18 Y22 AA3 AA7
Function
SysAD[52] Vcclnt SysAD[51] SysAD[45] SysAD[49] SysAD[15] SysAD[16] RspSwap* VccOK Vcclnt NMI* JTDO INT[9]* VcclO INT[6]* VsslO VcclO TcWord[0] Vcclnt VcclO VsslO VcclO ValidOut*
Pin
M22 N3 N22 P3 P22 R3 R22 T3 T22 U3 U22 V3 V22 W3 W22 Y3 Y7 Y11 Y15 Y19 Y23 AA4 AA8
Function
SysAD[21] SysAD[12] Vcclnt SysAD[14] SysAD[18] SysAD[47] SysAD[48] PRqst* BigEndlan ModeClock Reset* JTMS Vcclnt INT[8]* VcclO RdRdy* Vcclnt VcclO VcclO INT[7]* VcclO SysClock
Pin
M23 N4 N23 P4 P23 R4 R23 T4 T23 U4 U23 V4 V23 W23 Y4 Y8 Y12 Y16 Y20 AA1 AA5 AA9
Function
VsslO SysAD[44] SysAD[20] Vcclnt SysAD[50] VcclO SysAD[17] Vcclnt VsslO JTCK ColdReset* VcclO VsslO VcclO Vcclnt VcclO Release* VcclO Vcclnt VcclO VsslO Do Not Connect Vcclnt
Do Not Connect W4
Do Not Connect Y2
AA10 Do Not Connect AA11 Do Not Connect AA12 SysCmd[0] AA14 SysCmd[8] AA18 INT[3]* AA22 Vsslnt AB3 AB7 Vsslnt VccP AA15 TcTCE* AA23 VsslO AB4 AB8 VsslO Vcclnt AA16 TcValid AB1 AB5 AB9 VsslO Modeln Vcclnt AA19 Do Not Connect AA20 VcclO
AA13 SysCmd[4] AA17 Vcclnt AA21 VcclO AB2 AB6 VcclO Validin*
AB10 TcCWE[0]* AB14 SysCmd[7] AB18 INT[0]* AB22 VcclO AC3 AC7 VsslO VssP
AB11 TcDCE[0]* AB15 TcClr* AB19 INT[4]* AB23 Vsslnt AC4 AC8 RdType VsslO
AB12 SysCmd[1] AB16 TcTDE* AB20 VsslO AC1 AC5 AC9 VcclO WrRdy* TcWord[1]
AB13 SysCmd[3] AB17 TcDOE* AB21 Vsslnt AC2 AC6 Vsslnt VsslO
AC10 TcCWE[1]* AC14 SysCmd[6] AC18 VsslO AC22 VsslO
AC11 TcDCE[1]* AC15 SysCmdP AC19 INT[1]* AC23 VcclO
AC12 VsslO AC16 VsslO AC20 INT[5]*
AC13 SysCmd[2]* AC17 TcTOE* AC21 VsslO
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use Document ID: PMC-2002175, Issue 1
52
RM7000TM Microprocessor with On-Chip Secondary Cache Datasheet Released
14
Ordering Information
RM7000 -123 T I Temperature Grade: (blank) = commercial I = Industrial Package Type: T = TBGA S = SBGA
Device Maximum Speed Device Type Valid Combinations RM7000-200T RM7000-250T RM7000-266T RM7000-300T
Legacy Devices RM7000-200S RM7000-225S RM7000-250S RM7000-263S RM7000-300S
Recommended Conversions RM7000-200T RM7000-250T RM7000-250T RM7000-266T RM7000-300T
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use Document ID: PMC-2002175, Issue 1
53
RM7000TM Microprocessor with On-Chip Secondary Cache Datasheet Released
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use Document ID: PMC-2002175, Issue 1
54

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